1. Field of the Invention
This invention relates to reprogrammable non-volatile memory devices able to output stored digital information “1” or “0” without applying a sense amplifier. In particular, Complementary Electrical Erasable Programmable Read Only Memory (CEEPROM) is configured to a static stored signal of either VDD (“1”) or VSS (“0”) in the memory cell. The digital data in the memory cell are directly accessed by an access transistor without passing through a sense amplifier.
2. Description of the Related Art
In the digital world of electronic systems, Complementary Metal-Oxide Semiconductor (CMOS) process becomes the most popular fabrication process for Application Specific Integrated Circuit (ASIC). An ASIC contains the specific functionality of a device or a system on a single Integrated Circuit (IC) or a chip. Changes for the specific functionality or configurations are required in many applications. For example, the initial programming and configuring a microprocessor require a programmable and non-volatile memory to store the programmed instructions. The programmed instructions shall be allowed to change any time without changing the hardware during developments. This requirement for electronic systems is done by Electrically Erasable Programmable Read-Only Memory (EEPROM) device.
The conventional semiconductor EEPROM devices usually consist of a charge storing memory cell 120 and an access MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) 110 as the schematic shown in FIG. 1. The charge storing memory cell 120 is a MOSFET with a layer of charge storage material 122 under the control gate 124 and above the channel surface of a MOSFET. The amounts of charges in the storing layer 122 can affect the threshold voltage applied to the control gate 124 to turn on the channel of the MOSFET memory cell. For instance, the threshold voltage of N-type semiconductor memory cell shifts to a higher voltage from storing electrons (negative charge) in the charge storage layer. While the threshold voltage of P-type semiconductor memory cell shifts to a lower voltage from storing electrons (negative charge) in the charge storage layer. By injecting into the storing layer of the semiconductor memory cell to cause threshold voltage changes, the electrical conductance of the semiconductor memory cell is also altered, when applying a voltage bias to the control gate of the semiconductor memory cell. The semiconductor memory cells become non-volatile, if the charges in the storing layer can be retained for a long period of time (>10 years for a typical semiconductor non-volatile memory). If a non-volatile memory element can perform the cycles of erase/programming operations the non-volatile memory is Multiple Times Programming Non-Volatile Memory (MTPNVM). Usually, the numbers of erase/programming cycling for a semiconductor non-volatile memory are between thousands to millions times.
In the conventional scheme of reading out a stored bit in EEPROM as depicted in FIG. 2, the source and drain electrodes of the semiconductor memory cell 120 are connected to ground node and the source electrode of the access transistor 110, respectively. The drain electrode of the access transistor 110 is then attached to a bitline. The control gate of semiconductor memory cell 120 is biased with a constant voltage VCG. The access transistor 110 is activated to attach to the bitline by applying a voltage bias VG. A current source configured with a constant voltage bias VR to one node of a load device 220 and the other node connected to the bitline passes electrical current ICELL through the access transistor 110 to the ground node of the semiconductor memory cell 120. The cell current ICELL flowing through the memory cell varies according to the conductance of the memory cell altered by the threshold voltage change with a constant control gate voltage bias VCG. The cell current ICELL is then proportionally amplified by a current mirror circuitry 210. By comparing the amplified cell current with a reference current IREF, the bit information (“1” and “0”) is read out by a current comparator 230. That is, the output signal of the comparator 230 is VDD (logic“1”) for amplified cell current greater than the reference current or VSS (logic “0”) for amplified cell current less than reference current and vise versa. Since the DC currents including the amplified cell currents (cell current+mirror current) and the reference current are compared in the conventional readout scheme the required total sensing power is high. The DC current consumption is usually greater than 100 s μA per cell for a typical semiconductor non-volatile memory not including the switching currents of outputting “1” or “0”.
In this invention we apply two non-volatile memory elements and one access transistor to form a Complementary Electrical Erasable Programmable Read Only Memory (CEEPROM) cell. The CEEPROM outputs digital signals VDD (“1”) and VSS (“0”) without going through a sense amplifier. The digital datum from the CEEPROM can be fed into to digital circuitries directly. The CEEPROM can provide fast-access, simple, low power, and cost effective solutions for embedded re-configurable digital integrated circuitries.